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ADVANCED SOLID-STATE MEMORY SYSTEMS AND PRODUCTS: EMERGING NON-VOLATILE MEMORY TECHNOLOGIES, INDUSTRY TRENDS AND MARKET ANALYSIS
(View Introduction/Table Of Contents)
Publish Date: Apr 2011,   Pages: 146,   Report Code: ET-114
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1. INTRODUCTIONi-vii
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INTRODUCTION................................................................................................................................... I

STUDY GOAL AND OBJECTIVES..............................................................................................II

REASONS FOR DOING THE STUDY....................................................................................... III

CONTRIBUTIONS OF THE STUDY ..........................................................................................IV

SCOPE AND FORMAT ................................................................................................................IV

METHODOLOGY ..........................................................................................................................V

INFORMATION SOURCES.........................................................................................................VI

TO WHOM THE STUDY CATERS..............................................................................................VI

AUTHOR’S CREDENTIALS......................................................................................................VII

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2. EXECUTIVE SUMMARYviii-x
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EXECUTIVE SUMMARY................................................................................................................VIII

SUMMARY TABLE GLOBAL MARKET FOR EMERGING NON-VOLATILE

RANDOM ACCESS MEMORY PRODUCTS BY REGION THROUGH 2015...........................IX

SUMMARY FIGURE GLOBAL MARKET FOR EMERGING NON-VOLATILE

RANDOM ACCESS MEMORY PRODUCTS BY REGION, 2010 AND 2015 ............................. X

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3. INDUSTRY OVERVIEW1-3
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INDUSTRY OVERVIEW.....................................................................................................................1

LEADING MANUFACTURERS....................................................................................................1

LEADING MANUFACTURERS (CONTINUED) ............................................................2

FIGURE 1 EMERGING NON-VOLATILE RANDOM ACCESS MEORY

TECHNOLOGY SCENARIO IN 2010.............................................................................................3

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4. TECHNOLOGY OVERVIEW4-53
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TECHNOLOGY OVERVIEW................................................................................................................4

CURRENT NON-VOLATILE MEMORIES ..................................................................................4

EMERGING NVM...........................................................................................................................5

EMERGING NVM (CONTINUED) ..................................................................................6

TYPES OF TECHNOLOGIES .......................................................................................................7

TABLE 1 COMPARISON OF EMERGING NON-VOLATILE RANDOM ACCESS

MEMORIES.....................................................................................................................................8

TABLE 2 DEFINITIONS AND EXPLANATION OF TERMINOLOGIES

APPLICABLE TO EMERGING NON-VOLATILE MEMORIES..................................................9

TABLE 2 (CONTINUED) .....................................................................................................................10

TABLE 2 (CONTINUED) .....................................................................................................................11

TABLE 2 (CONTINUED) .....................................................................................................................12

TABLE 2 (CONTINUED) .....................................................................................................................13

TABLE 2 (CONTINUED) .....................................................................................................................14

EVOLUTION OF EMERGING NON-VOLATILE RANDOM ACCESS

MEMORY TECHNOLOGIES................................................................................................15

BACKGROUND OF SEMICONDUCTOR MEMORY...................................................15

MEMORY USAGE AND APPLICATIONS ....................................................................16

MEMORY MARKET SEGMENTS .................................................................................16

NON-VOLATILE SEMICONDUCTOR MEMORY

(NVSM)/STORAGE-CLASS MEMORY (SCM) VERSUS

EMERGING NON-VOLATILE MEMORIES ..........................................................17

EMERGING NON-VOLATILE MEMORY TECHNOLOGIES.....................................18

EMERGING NON-VOLATILE MEMORY TECHNOLOGIES

(CONTINUED) .............................................................................................19

ADVANTAGES OF EMERGING NVMS OVER CONVENTIONAL

NVMS.........................................................................................................................20

FIGURE 2 FLOATING-GATE POLYSILICON (FLASH) ARCHITECTURE.................................21

DESCRIPTION OF EMERGING NON-VOLATILE RANDOM ACCESS

MEMORIES ............................................................................................................................22

FERROMAGNETIC RANDOM ACCESS MEMORY (FERAM) ...................................22

FIGURE 3 FERROELECTRIC CRYSTALS SHOWING MOBILE ATOM

MOVING IN DIRECTION OF APPLIED FIELD SETTING A DIGITAL

STATE-0 ........................................................................................................................................23

PHASE CHANGE RANDOM ACCESS MEMORY (PCRAM) ......................................24

FIGURE 4 A VIEW OF PHASE CHANGE MEMORY.....................................................................25

FIGURE 5 OPERATION OF PCRAM................................................................................................26

FIGURE 6 SET AND RESET OPERATION IN PCM......................................................................27

CHARACTERISTICS .........................................................................................28

BENEFITS ..........................................................................................................28

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) .............................29

DENSITY.............................................................................................................30

POWER CONSUMPTION..................................................................................31

SPEED.................................................................................................................32

OVERALL............................................................................................................32

FIGURE 7 OPERATION OF MAGNETO-RESISTIVE RANDOM ACCESS

MEMORY.......................................................................................................................................33

RACETRACK MEMORY: A VARIANT OF MRAM..........................................34

FIGURE 8 OPERATION OF RACETRACK RANDOM ACCESS MEMORY .................................35

COMPARISON TO OTHER MEMORY DEVICES ..........................................36

DEVELOPMENT DIFFICULTIES....................................................................37

RESISTIVE SWITCHING RANDOM ACCESS MEMORY (RRAM) ...........................38

FIGURE 9 CONSTUCTION OF RESISTIVE RANDOM ACCESS MEMORY .............................38

RESISTIVE SWITCHING RANDOM ACCESS MEMORY

(RRAM)..........................................................................................................39

A VARIANT OF RRAM: PROGRAMMABLE

METALLIZATION CELL (PMC) ................................................................40

CBRAM VERSUS RRAM................................................................................................41

COMPARISONS .................................................................................................41

CURRENT STATUS...........................................................................................42

CMOX: A VARIANT OF RRAM.........................................................................42

CONDUCTIVE METAL OXIDES......................................................................43

NANO-RAM: A VARIANT OF RRAM............................................................................44

FIGURE 10 ARCHITECTURE OF NANO RANDOM ACCESS MEMORY ...................................45

ADVANTAGES OF NRAM ...................................................................46

COMPARISON WITH OTHER PROPOSED

SYSTEMS ........................................................................................47

MEMRISTORS: A VARIANT OF RRAM ..........................................................48

ZERO CAPACITOR RANDOM ACCESS MEMORY.....................................................48

QUANTUM DOT RANDOM ACCESS MEMORY.........................................................49

POLYMER PRINTED MEMORY ...................................................................................50

FIGURE 11 A VIEW OF FERROELECTRIC POLYMER MEMORY..............................................51

POLYMER PRINTED MEMORY (CONTINUED) ...........................................52

POLYMER PRINTED MEMORY (CONTINUED) ...........................................53

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5. APPLICATIONS OF EMERGING NON-VOLATILE MEMORY PRODUCTS54-63
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APPLICATIONS OF EMERGING NON-VOLATILE MEMORY PRODUCTS .....................................54

STORAGE-CLASS MEMORY......................................................................................................54

COMPUTE-CENTRIC WORKLOADS ...........................................................................54

DATA-CENTRIC WORKLOADS....................................................................................55

TABLE 3 STORAGE-CLASS MEMORY V/S DISK MEMORY REQUIREMENT

FORECAST IN 2020 ......................................................................................................................56

SMART AIRBAGS ........................................................................................................................57

RADIATION-HARDENED MEMORY APPLICATIONS...........................................................58

RADIO-FREQUENCY IDENTIFICATION (RFID) ....................................................................58

SMART MOBILE PHONES.........................................................................................................59

PRINTED MEMORY PLATFORMS............................................................................................59

EMBEDDED MEMORY...............................................................................................................60

EMBEDDED MEMORY (CONTINUED) .......................................................................61

FIGURE 12 EMERGING MEMORY MANUFACTURING TECHNOLOGY AND

CONVENTIONAL CMOS TECHNOLOGY..................................................................................62

ORGANIC SWITCHING MATERIALS..........................................................................63

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6. INDUSTRY STRUCTURE AND MARKETS64-68
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INDUSTRY STRUCTURE AND MARKETS ......................................................................................64

TABLE 4 NON-VOLATILE EMERGING MEMORIES MANUFACTURERS,

MATERIAL SUPPLIERS, END USERS AND SYSTEM INTEGRATORS ..............................65

PARTNERSHIPS AND CONSOLIDATIONS.............................................................................66

TABLE 5 ACQUISITIONS, MERGERS AND PARTNERSHIPS IN EMERGING

NON-VOLATILE MEMORIES .....................................................................................................67

PRICE STRUCTURE....................................................................................................................68

TABLE 6 COMMERCIALLY AVAILABLE NON-VOLATILE EMERGING

MEMORY CHIPS IN 2010 ............................................................................................................68

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7. GLOBAL MARKET AND REGIONAL SHARES69-75
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GLOBAL MARKET AND REGIONAL SHARES.................................................................................69

MARKET ACCORDING TO APPLICATIONS ...........................................................................69

TABLE 7 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

APPLICATION THROUGH 2015 .................................................................................................70

FIGURE 13 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

APPLICATION THROUGH 2015 .................................................................................................71

MARKET BY TECHNOLOGY.....................................................................................................72

TABLE 8 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

TECHNOLOGIES ADOPTED THROUGH 2015.........................................................................72

FIGURE 14 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

TECHNOLOGIES ADOPTED IN 2010 ........................................................................................73

REGIONAL MARKETS................................................................................................................74

TABLE 9 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

REGION THROUGH 2015............................................................................................................74

FIGURE 15 GLOBAL MARKET FOR EMERGING NVRAM PRODUCTS BY

REGION THROUGH 2015............................................................................................................75

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8. PATENTS AND PATENT ANALYSIS76-122
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PATENTS AND PATENT ANALYSIS ................................................................................................76

LIST OF PATENTS ......................................................................................................................76

PHASE CHANGE RANDOM ACCESS MEMORY DEVICES AND

METHODS OF OPERATING THE SAME..............................................................76

METHODS FOR FABRICATING PHASE CHANGEABLE MEMORY

DEVICES ...................................................................................................................76

PHASE CHANGE DEVICE HAVING TWO OR MORE

SUBSTANTIAL AMORPHOUS REGIONS IN HIGH

RESISTANCE STATE ..............................................................................................76

NON-VOLATILE MEMORY INCLUDING SUB-CELL ARRAY AND

METHOD OF WRITING DATA THERETO............................................................76

MEMORY CELL DEVICE AND PROGRAMMING METHODS..................................77

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND

RELATED METHODS OF OPERATION................................................................77

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE.........................................77

MULTI-LEVEL CELL RESISTANCE RANDOM ACCESS MEMORY

WITH METAL OXIDES............................................................................................77

MEMORY CELL WITH MEMORY MATERIAL INSULATION AND

MANUFACTURING METHOD ...............................................................................77

MULTI-LEVEL MEMORY CELL HAVING PHASE CHANGE

ELEMENT AND ASYMMETRICAL THERMAL BOUNDARY.............................77

MULTILAYER STORAGE CLASS MEMORY USING EXTERNALLY

HEATED PHASE CHANGE MATERIAL ...............................................................77

MAGNETIC RAM............................................................................................................78

PHASE CHANGE MEMORY CELL AND MANUFACTURING

METHOD ...................................................................................................................78

VACUUM-JACKETED ELECTRODE FOR PHASE CHANGE

MEMORY ELEMENT...............................................................................................78

METHOD FOR MAKING A KEYHOLE OPENING DURING THE

MANUFACTURE OF A MEMORY CELL...............................................................78

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE........................................78

METHOD FOR READING NON-VOLATILE FERROELECTRIC

CAPACITOR MEMORY CELL.................................................................................78

RESISTANCE MEMORY ELEMENT AND NONVOLATILE

SEMICONDUCTOR MEMORY ...............................................................................78

RESISTANCE MEMORY ELEMENT AND NONVOLATILE

SEMICONDUCTOR MEMORY ...............................................................................79

METHOD TO IMPROVE FERROELECTRONIC MEMORY

PERFORMANCE AND RELIABILITY ...................................................................79

MULTI-PORT PHASE CHANGE RANDOM ACCESS MEMORY

CELL AND MULTI-PORT PHASE CHANGE RANDOM ACCESS

MEMORY DEVICE INCLUDING THE SAME.......................................................79

MEMORY CELL HAVING A SIDE ELECTRODE CONTACT....................................79

MAGNETIC MEMORIES UTILIZING A MAGNETIC ELEMENT

HAVING AN ENGINEERED FREE LAYER..........................................................79

PROGRAMMABLE LOGIC DEVICE STRUCTURE USING THIRD

DIMENSIONAL MEMORY......................................................................................79

2T/2C FERROELECTRIC RANDOM ACCESS MEMORY WITH

COMPLEMENTARY BIT-LINE LOADS.................................................................80

NON-VOLATILE FERROELECTRIC MEMORY..........................................................80

FIELD PROGRAMMABLE GATE ARRAYS USING RESISTIVITY

SENSITIVE MEMORIES .........................................................................................80

BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF

MEMORY IN INTEGRATED CIRCUITS................................................................80

PHASE CHANGE MEMORY CELL HAVING INTERFACE

STRUCTURES WITH ESSENTIALLY EQUAL THERMAL

IMPEDANCES AND MANUFACTURING METHODS.........................................80

THIN-FILM FUSE PHASE CHANGE CELL WITH THERMAL

ISOLATION PAD AND MANUFACTURING METHOD.......................................80

METHOD OF WRITING INTO SEMICONDUCTOR MEMORY

DEVICE......................................................................................................................81

PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELFALIGNED,

SELF-CONVERGED BOTTOM ELECTRODE AND

METHOD FOR MANUFACTURING ......................................................................81

THERMALLY INSULATED PHASE CHANGE MEMORY

MANUFACTURING METHOD ...............................................................................81

PHASE CHANGE RANDOM ACCESS MEMORY (PRAM) DEVICE .........................81

PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND

MANUFACTURING METHODS.............................................................................81

METHOD FOR MAKING A SELF-CONVERGED VOID AND

BOTTOM ELECTRODE FOR MEMORY CELL.....................................................81

I-SHAPED PHASE CHANGE MEMORY CELL ...........................................................82

MULTI-RESISTIVE STATE MEMORY DEVICE WITH

CONDUCTIVE OXIDE ELECTRODES ..................................................................82

PLANAR THIRD DIMENSIONAL MEMORY WITH MULTI-PORT

ACCESS .....................................................................................................................82

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE........................................82

MAGNETORESISTIVE RANDOM ACCESS MEMORY AND ITS

WRITE CONTROL METHOD..................................................................................82

METHODS AND SYSTEMS FOR ACCESSING MEMORY.........................................82

SPACE AND PROCESS EFFICIENT MRAM AND METHOD....................................82

OPTIMIZED PHASE CHANGE WRITE METHOD......................................................83

PHASE-CHANGE RANDOM ACCESS MEMORY AND

PROGRAMMING METHOD....................................................................................83

MEMORY DEVICE, IN PARTICULAR PHASE CHANGE RANDOM

ACCESS MEMORY DEVICE WITH TRANSISTOR, AND

METHOD FOR FABRICATING A MEMORY DEVICE.........................................83

MEMORY POWER MANAGEMENT.............................................................................83

MULTI-STEP SELECTIVE ETCHING FOR CROSS-POINT

MEMORY...................................................................................................................83

RESISTIVE RANDOM ACCESS MEMORY DEVICE..................................................83

MEMORY CELL DEVICE WITH COPLANAR ELECTRODE

SURFACE AND METHOD.......................................................................................83

PROGRAMMABLE RESISTIVE MEMORY CELL WITH SELFFORMING

GAP.........................................................................................................84

BRIDGE RESISTANCE RANDOM ACCESS MEMORY DEVICE

WITH A SINGULAR CONTACT STRUCTURE .....................................................84

SIDE WALL ACTIVE PIN MEMORY AND MANUFACTURING

METHOD ...................................................................................................................84

MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING

TWO ACCESS TRANSISTORS................................................................................84

MANUFACTURING METHOD FOR PHASE CHANGE RAM WITH

ELECTRODE LAYER PROCESS ............................................................................84

MEMORY CELL DEVICE AND MANUFACTURING METHOD ...............................84

THIN-FILM FUSE PHASE CHANGE CELL WITH THERMAL

ISOLATION LAYER AND MANUFACTURING METHOD..................................84

METHODS AND APPARATUS FOR A DUAL-METAL MAGNETIC

SHIELD STRUCTURE .............................................................................................85

PROGRAMMABLE RESISTIVE RAM AND MANUFACTURING

METHOD ...................................................................................................................85

MEMORY EMULATION USING RESISTIVITY-SENSITIVE

MEMORY...................................................................................................................85

METHODS OF OPERATING A BI-STABLE RESISTANCE

RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY

LAYERS AND MULTILEVEL MEMORY STATES ...............................................85

COMPOSITIONS FOR REMOVAL OF PROCESSING BYPRODUCTS

AND METHOD FOR USING SAME..................................................85

THIN-FILM FUSE PHASE CHANGE RAM AND

MANUFACTURING METHOD ...............................................................................85

PHASE CHANGE RANDOM ACCESS MEMORY AND METHOD OF

TESTING THE SAME ..............................................................................................86

PHASE-CHANGE RANDOM ACCESS MEMORY (PRAM)

PERFORMING PROGRAM LOOP OPERATION AND METHOD

OF PROGRAMMING THE SAME...........................................................................86

PHASE CHANGE MATERIALS, PHASE CHANGE RANDOM

ACCESS MEMORIES HAVING THE SAME AND METHODS OF

OPERATING PHASE CHANGE RANDOM ACCESS

MEMORIES...............................................................................................................86

PHASE-CHANGE MEMORY DEVICE INCLUDING NANOWIRES

AND METHOD OF MANUFACTURING THE SAME...........................................86

MEMORY CELL SIDEWALL CONTACTING SIDE ELECTRODE............................86

FERROELECTRIC MEMORY ARRAY FOR IMPLEMENTING A

ZERO CANCELLATION SCHEME TO REDUCE PLATELINE

VOLTAGE IN FERROELECTRIC MEMORY.........................................................86

PROGRAMMABLE RESISTIVE RAM AND MANUFACTURING

METHOD ...................................................................................................................87

METHOD OF CONTROLLING THE RESISTANCE IN A VARIABLE

RESISTIVE ELEMENT AND NON-VOLATILE

SEMICONDUCTOR MEMORY DEVICE................................................................87

MEMORY DEVICE AND MANUFACTURING METHOD ..........................................87

PROGRAMMABLE RESISTIVE MEMORY WITH DIODE

STRUCTURE.............................................................................................................87

PHASE CHANGE RANDOM ACCESS MEMORY .......................................................87

MRAM READ BIT WITH ASKEW FIXED LAYER ......................................................87

RESISTIVE MEMORY DEVICE ....................................................................................87

SEMICONDUCTOR MEMORY DEVICE ......................................................................88

SCALEABLE MEMORY SYSTEMS USING THIRD DIMENSION

MEMORY...................................................................................................................88

MEMORY USING VARIABLE TUNNEL BARRIER WIDTHS ...................................88

TOGGLE MEMORY BURST...........................................................................................88

MAGNETIC TUNNEL JUNCTION WITH ENHANCED MAGNETIC

SWITCHING CHARACTERISTICS ........................................................................88

METHOD TO TIGHTEN SET DISTRIBUTION FOR PCRAM....................................88

PHASE CHANGE RANDOM ACCESS MEMORY AND RELATED

METHODS OF OPERATION...................................................................................88

DAMASCENE PHASE CHANGE RAM AND MANUFACTURING

METHOD ...................................................................................................................89

METHOD FOR FORMING SELF-ALIGNED THERMAL

ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY

ARRAY .......................................................................................................................89

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND

METHOD OF WRITING INTO THE SAME...........................................................89

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE.............................................89

CONDUCTIVE MEMORY STACK WITH SIDEWALL................................................89

METHOD FOR MANUFACTURING A RESISTOR RANDOM

ACCESS MEMORY WITH REDUCED ACTIVE AREA AND

REDUCED CONTACT AREAS................................................................................89

SERIAL MEMORY INTERFACE...................................................................................89

FERROELECTRIC RANDOM ACCESS MEMORIES (FRAMS)

HAVING LOWER ELECTRODES RESPECTIVELY SELF

ALIGNED TO NODE CONDUCTIVE LAYER PATTERNS AND

METHODS OF FORMING THE SAME ..................................................................90

SURFACE TOPOLOGY IMPROVEMENT METHOD FOR PLUG

SURFACE AREAS ....................................................................................................90

GE PRECURSOR, GST THIN LAYER FORMED USING THE

SAME, PHASE-CHANGE MEMORY DEVICE INCLUDING THE

GST THIN LAYER, AND METHOD OF MANUFACTURING

THE GST THIN LAYER...........................................................................................90

HARDMASK FOR FORMING FERROELECTRIC CAPACITORS IN

A SEMICONDUCTOR DEVICE AND METHODS FOR

FABRICATING THE SAME.....................................................................................90

CURRENT COMPLIANT SENSING ARCHITECTURE FOR

MULTILEVEL PHASE CHANGE MEMORY.........................................................90

METHOD FOR MANUFACTURING A NARROW STRUCTURE ON

AN INTEGRATED CIRCUIT ...................................................................................90

THIN-FILM PLATE PHASE CHANGE RAM CIRCUIT AND

MANUFACTURING METHOD ...............................................................................91

MANUFACTURING METHODS FOR THIN-FILM FUSE PHASE

CHANGE RAM..........................................................................................................91

METHOD FOR MAKING MEMORY CELL DEVICE ..................................................91

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND

DATA WRITING METHOD .....................................................................................91

THERMAL ISOLATION FOR AN ACTIVE-SIDEWALL PHASE

CHANGE MEMORY CELL ......................................................................................91

METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT IN

MRAM INTEGRATION............................................................................................91

METHOD FOR SENSING A SIGNAL IN A TWO-TERMINAL

MEMORY ARRAY HAVING LEAKAGE CURRENT.............................................92

MEMORY CELL DEVICE WITH CIRCUMFERENTIALLYEXTENDING

MEMORY ELEMENT.......................................................................92

PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY

DEVICES ...................................................................................................................92

NONVOLATILE MEMORY WITH DATA CLEARING

FUNCTIONALITY ....................................................................................................92

PHASE-CHANGE RANDOM ACCESS MEMORY EMPLOYING

READ BEFORE WRITE FOR RESISTANCE STABILIZATION..........................92

MEMORY DEVICES HAVING SHARP-TIPPED PHASE CHANGE

LAYER PATTERNS ..................................................................................................92

METHOD AND APPARATUS FOR REFRESHING

PROGRAMMABLE RESISTIVE MEMORY ...........................................................93

MEMORY CELL WITH SEPARATE READ AND PROGRAM PATHS.......................93

VACUUM JACKETED ELECTRODE FOR PHASE CHANGE

MEMORY ELEMENT...............................................................................................93

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE AND

METHOD OF DRIVING THE SAME ......................................................................93

METHOD FOR MAKING A SELF-CONVERGED MEMORY

MATERIAL ELEMENT FOR MEMORY CELL......................................................93

TWO-ELEMENT MAGNETIC MEMORY CELL ..........................................................93

METHOD FOR PRODUCTION OF MRAM ELEMENTS ............................................93

THERMALLY INSULATED PHASE CHANGE MEMORY DEVICE .........................94

MULTI-STATE MAGNETORESISTANCE RANDOM ACCESS CELL

WITH IMPROVED MEMORY STORAGE DENSITY ............................................94

MEMORY ELEMENT WITH REDUCED-CURRENT PHASE

CHANGE ELEMENT................................................................................................94

PHASE CHANGE MEMORY CELL AND MANUFACTURING

METHOD ...................................................................................................................94

TWO-TERMINAL MEMORY ARRAY HAVING REFERENCE

CELLS........................................................................................................................94

PHASE CHANGE RANDOM ACCESS MEMORY (PRAM) DEVICE

HAVING VARIABLE DRIVE VOLTAGES .............................................................94

VACUUM JACKET FOR PHASE CHANGE MEMORY ELEMENT...........................94

PHASE CHANGE MEMORY DEVICE AND MANUFACTURING

METHOD ...................................................................................................................95

SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A

MELTING POINT IN A RESISTOR RANDOM ACCESS

MEMORY...................................................................................................................95

WRITE DRIVER CIRCUIT FOR CONTROLLING A WRITE

CURRENT APPLIED TO A PHASE CHANGE MEMORY BASED

ON AN AMBIENT TEMPERATURE.......................................................................95

METHOD FOR TWO-CYCLE SENSING IN A TWO-TERMINAL

MEMORY ARRAY HAVING LEAKAGE CURRENT.............................................95

CONDUCTIVE MEMORY STACK WITH NON-UNIFORM WIDTH .........................95

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND

METHOD OF OPERATING THE SAME ................................................................95

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT

FOR STEPPED RESET PROGRAMMING PROCESS ON

PROGRAMMABLE RESISTIVE MEMORY CELL ................................................96

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE.........................................96

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT

FOR READ BEFORE PROGRAMMING PROCESS ON

MULTIPLE PROGRAMMABLE RESISTIVE MEMORY CELL ...........................96

VERTICAL SIDE WALL ACTIVE PIN STRUCTURES IN A PHASE

CHANGE MEMORY AND MANUFACTURING METHODS................................96

SINGLE-MASK PHASE CHANGE MEMORY ELEMENT..........................................96

SELF-ALIGNED MANUFACTURING METHOD, AND

MANUFACTURING METHOD FOR THIN-FILM FUSE PHASE

CHANGE RAM..........................................................................................................96

FERROELECTRIC RANDOM ACCESS MEMORY......................................................97

PHASE CHANGE MEMORY HAVING MULTILAYER THERMAL

INSULATION............................................................................................................97

SPACER ELECTRODE SMALL PIN PHASE CHANGE MEMORY

RAM AND MANUFACTURING METHOD ............................................................97

SEMICONDUCTOR STORAGE DEVICE .....................................................................97

MEMORY WRITE CIRCUIT ..........................................................................................97

RESISTANCE RANDOM ACCESS MEMORY DEVICES AND

METHOD OF FABRICATION .................................................................................97

CONDUCTIVE MEMORY DEVICE WITH CONDUCTIVE OXIDE

ELECTRODES ..........................................................................................................97

MAGNETIC DEVICES AND TECHNIQUES FOR FORMATION

THEREOF..................................................................................................................98

RESISTIVE MEMORY DEVICE ....................................................................................98

PIPE SHAPED PHASE CHANGE MEMORY...............................................................98

MULTI-RESISTIVE STATE ELEMENT WITH REACTIVE METAL.........................98

THERMALLY CONTAINED/INSULATED PHASE CHANGE

MEMORY DEVICE AND METHOD (COMBINED) ...............................................98

METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM

ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND

MULTILEVEL MEMORY STATES.........................................................................98

SPACER CHALCOGENIDE MEMORY DEVICE.........................................................98

TWO-TERMINAL MEMORY ARRAY HAVING REFERENCE

CELLS........................................................................................................................99

METHOD OF MAKING THREE-DIMENSIONAL, 2R MEMORY

HAVING A 4F2 CELL SIZE RRAM.........................................................................99

SENSING A SIGNAL IN A TWO-TERMINAL MEMORY ARRAY

HAVING LEAKAGE CURRENT .............................................................................99

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE.............................................99

FERROELECTRIC RANDOM ACCESS MEMORY CIRCUITS FOR

GUARDING AGAINST OPERATION WITH OUT-OF-RANGE

VOLTAGES AND METHODS OF OPERATING SAME........................................99

FERROELECTRIC RANDOM ACCESS MEMORIES (FRAMS)

HAVING LOWER ELECTRODES RESPECTIVELY SELFALIGNED

TO NODE CONDUCTIVE LAYER PATTERNS AND

METHODS OF FORMING THE SAME ..................................................................99

TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY

HAVING LEAKAGE CURRENT ...........................................................................100

FERROELECTRIC RANDOM ACCESS MEMORY CAPACITOR

AND METHOD FOR MANUFACTURING THE SAME ......................................100

STRAIN CONTROL OF EPITAXIAL OXIDE FILMS USING

VIRTUAL SUBSTRATES .......................................................................................100

SEPARATE WRITE AND READ ACCESS ARCHITECTURE FOR A

MAGNETIC TUNNEL JUNCTION.......................................................................100

FERROELECTRIC CAPACITOR WITH PARALLEL RESISTANCE

FOR FERROELECTRIC MEMORY.......................................................................100

APPARATUS FOR PULSE TESTING A MRAM DEVICE AND

METHOD THEREFORE ........................................................................................100

ENHANCED FUNCTIONALITY IN A TWO-TERMINAL MEMORY

ARRAY .....................................................................................................................101

LOW POWER MAGNETORESISTIVE RANDOM ACCESS

MEMORY ELEMENTS...........................................................................................101

STORAGE CONTROLLER FOR MULTIPLE CONFIGURATIONS

OF VERTICAL MEMORY ......................................................................................101

RESISTIVE MEMORY DEVICE WITH A TREATED INTERFACE.........................101

PROVIDING A REFERENCE VOLTAGE TO A CROSS POINT

MEMORY ARRAY...................................................................................................101

INITIALIZING PHASE CHANGE MEMORIES .........................................................101

PHASE CHANGE RANDOM ACCESS MEMORY, BOOSTING

CHARGE PUMP AND METHOD OF GENERATING WRITE

DRIVING VOLTAGE ..............................................................................................101

THIN-FILM FUSE PHASE CHANGE RAM AND

MANUFACTURING METHOD .............................................................................102

CONTROL OF SET/RESET PULSE IN RESPONSE TO

PERIPHERAL TEMPERATURE IN PRAM DEVICE..........................................102

FERROELECTRIC MEMORY DEVICES HAVING A PLATE LINE

CONTROL CIRCUIT ..............................................................................................102

LASER ANNEALING OF COMPLEX METAL OXIDES (CMO)

MEMORY MATERIALS FOR NON-VOLATILE MEMORY

INTEGRATED CIRCUITS .....................................................................................102

READ BIAS SCHEME FOR PHASE CHANGE MEMORIES....................................102

FERROELECTRIC MEMORY WITH WIDE OPERATING VOLTAGE

AND MULTI-BIT STORAGE PER CELL..............................................................102

CIRCUITS FOR DRIVING FRAM................................................................................102

FERROELECTRIC RANDOM ACCESS MEMORY....................................................103

INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY ..................................103

SERIAL TRANSISTOR-CELL ARRAY ARCHITECTURE ........................................103

PHASE CHANGE RANDOM ACCESS MEMORY DEVICE HAVING

VARIABLE DRIVE VOLTAGE CIRCUIT.............................................................103

CHAIN FERROELECTRIC RANDOM ACCESS MEMORY (CFRAM)

HAVING AN INTRINSIC TRANSISTOR CONNECTED IN

PARALLEL WITH A FERROELECTRIC CAPACITOR ......................................103

MAGNETIC FILM STRUCTURE USING SPIN CHARGE, A

METHOD OF MANUFACTURING THE SAME, A

SEMICONDUCTOR DEVICE HAVING THE SAME, AND A

METHOD OF OPERATING THE SEMICONDUCTOR DEVICE.......................103

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE...........................................103

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE....................................104

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY

SIMULATION .........................................................................................................104

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND

METHOD FOR MANUFACTURING THE SAME ...............................................104

MRAM READ SEQUENCE USING CANTED BIT

MAGNETIZATION .................................................................................................104

NONVOLATILE MEMORY SYSTEM USING MAGNETORESISTIVE

RANDOM ACCESS MEMORY (MRAM)..........................................104

THIN-FILM PLATE PHASE CHANGE RAM CIRCUIT AND

MANUFACTURING METHOD .............................................................................104

CROSS-POINT RRAM MEMORY ARRAY HAVING LOW BIT LINE

CROSSTALK ...........................................................................................................104

DRIVING METHOD OF VARIABLE RESISTANCE ELEMENT AND

MEMORY DEVICE.................................................................................................105

TWO-TERMINAL MEMORY ARRAY HAVING REFERENCE

CELLS......................................................................................................................105

CROSS-POINT MEMORY ARRAY WITH FAST ACCESS TIME .............................105

PHASE CHANGE RANDOM ACCESS MEMORY (PRAM) DEVICE .......................105

MAGNETIC ELEMENT UTILIZING SPIN-TRANSFER AND HALFMETALS

AND AN MRAM DEVICE USING THE MAGNETIC

ELEMENT ...............................................................................................................105

SYNTHETIC ANTIFERROMAGNET STRUCTURES FOR USE IN

MTJS IN MRAM TECHNOLOGY..........................................................................105

FERROELECTRIC CAPACITOR STACK ETCH CLEANING

METHODS...............................................................................................................105

METHOD FOR MANUFACTURING MAGNETO-RESISTIVE

RANDOM ACCESS MEMORY...............................................................................106

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE AND

METHOD FOR DRIVING THE SAME..................................................................106

SELF-ALIGNED SMALL CONTACT PHASE-CHANGE MEMORY

METHOD AND DEVICE........................................................................................106

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF

MANUFACTURING THE SAME ..........................................................................106

METHOD OF PATTERNING A MAGNETIC TUNNEL JUNCTION

STACK FOR A MAGNETO-RESISTIVE RANDOM ACCESS

MEMORY.................................................................................................................106

CHEMICAL MECHANICAL POLISH OF PCMO THIN-FILMS FOR

RRAM APPLICATIONS..........................................................................................106

MRAM MEMORY WITH RESIDUAL WRITE FIELD RESET..................................107

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY AND

DRIVING METHOD THEREOF............................................................................107

PLATELINE VOLTAGE PULSING TO REDUCE STORAGE NODE

DISTURBANCE IN FERROELECTRIC MEMORY.............................................107

SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY

CELL ARRAY SHARED BY A PLURALITY OF MEMORY CELL

ARRAYS...................................................................................................................107

METHOD FOR PRODUCTION OF MRAM ELEMENTS ..........................................107

CONDUCTIVE MEMORY STACK WITH SIDEWALL..............................................107

MAGNETIC SWITCHING WITH EXPANDED HARD-AXIS

MAGNETIZATION VOLUME AT MAGNETO-RESISTIVE BIT

ENDS........................................................................................................................107

METHOD AND SYSTEM FOR PROVIDING CURRENT BALANCED

WRITING FOR MEMORY CELLS AND MAGNETIC DEVICES.......................108

FERROELECTRIC CAPACITOR HYDROGEN BARRIERS AND

METHODS FOR FABRICATING THE SAME .....................................................108

ETCH-STOP MATERIAL FOR IMPROVED MANUFACTURE OF

MAGNETIC DEVICES ...........................................................................................108

BIT END DESIGN FOR PSEUDO SPIN VALVE (PSV) DEVICES ..........................108

FERROELECTRIC CAPACITOR WITH PARALLEL RESISTANCE

FOR FERROELECTRIC MEMORY.......................................................................108

ONE-MASK PT/PCMO/PT STACK ETCHING PROCESS FOR RRAM

APPLICATIONS......................................................................................................108

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY DEVICES

AND METHODS FOR FABRICATING THE SAME............................................109

DEVICE AND METHOD FOR GENERATING REFERENCE

VOLTAGE IN FERROELECTRIC RANDOM ACCESS MEMORY

(FRAM) .....................................................................................................................109

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF

READING DATA.....................................................................................................109

LINE DRIVER THAT FITS WITHIN A SPECIFIED LINE PITCH..........................109

METHOD OF SUBSTRATE SURFACE TREATMENT FOR RRAM

THIN-FILM DEPOSITION ....................................................................................109

TRIPLE PULSE METHOD FOR MRAM TOGGLE BIT

CHARACTERIZATION...........................................................................................109

FERROELECTRIC CAPACITOR HAVING A SUBSTANTIALLY

PLANAR DIELECTRIC LAYER AND A METHOD OF

MANUFACTURE THEREFOR..............................................................................109

MRAM ARCHITECTURE WITH ELECTRICALLY ISOLATED

READ AND WRITE CIRCUITRY ..........................................................................110

MEMORY ARRAY OF A NON-VOLATILE RAM .......................................................110

PROVIDING A REFERENCE VOLTAGE TO A CROSS POINT

MEMORY ARRAY...................................................................................................110

FERROELECTRIC CAPACITOR AND METHOD FOR

MANUFACTURING THE SAME ..........................................................................110

SERIAL TRANSISTOR-CELL ARRAY ARCHITECTURE ........................................110

METHODS FOR FABRICATING A MAGNETIC KEEPER FOR A

MEMORY DEVICE.................................................................................................110

METHOD AND APPARATUS TO REDUCE STORAGE NODE

DISTURBANCE IN FERROELECTRIC MEMORY.............................................110

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY DEVICE

STRUCTURES AND METHODS FOR FABRICATING THE

SAME .......................................................................................................................111

NON-VOLATILE MEMORY WITH A SINGLE TRANSISTOR AND

RESISTIVE MEMORY ELEMENT .......................................................................111

REFERENCE VOLTAGE GENERATING APPARATUS FOR USE IN

A FERROELECTRIC RANDOM ACCESS MEMORY (FRAM)

AND A DRIVING METHOD THEREFOR ............................................................111

ARCHITECTURES FOR CPP RING SHAPED (RS) DEVICES.................................111

CONDUCTIVE MEMORY ARRAY HAVING PAGE MODE AND

BURST MODE WRITE CAPABILITY...................................................................111

RE-WRITABLE MEMORY WITH MULTIPLE MEMORY LAYERS ........................111

MULTI-STATE MAGNETO-RESISTANCE RANDOM ACCESS

CELL WITH IMPROVED MEMORY STORAGE DENSITY ...............................112

FERROELECTRIC MEMORY DEVICE ......................................................................112

SPIN BARRIER ENHANCED MAGNETO-RESISTANCE EFFECT

ELEMENT AND MAGNETIC MEMORY USING THE SAME...........................112

MULTI-RESISTIVE STATE ELEMENT WITH REACTIVE METAL.......................112

LAYOUT OF DRIVER SETS IN A CROSS-POINT MEMORY ARRAY....................112

CIRCUIT AND METHOD FOR REDUCING FATIGUE IN

FERROELECTRIC MEMORIES............................................................................112

METHOD AND APPARATUS FOR SIMULATING A MAGNETORESISTIVE

RANDOM ACCESS MEMORY (MRAM)..........................................112

TWO-TERMINAL MEMORY ARRAY HAVING REFERENCE

CELLS......................................................................................................................113

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE AND

CONTROL METHOD THEREOF..........................................................................113

MULTI-RESISTIVE STATE MATERIAL THAT USES DOPANTS..........................113

CONDUCTIVE MEMORY DEVICE WITH CONDUCTIVE OXIDE

ELECTRODES ........................................................................................................113

PCMO THIN-FILM WITH RESISTANCE RANDOM ACCESS

MEMORY (RRAM) CHARACTERISTICS.............................................................113

SEMICONDUCTOR STORAGE DEVICE ...................................................................113

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND

METHOD FOR MANUFACTURING THE SAME ...............................................113

LOW TEMPERATURE DEPOSITION OF COMPLEX METAL

OXIDES (CMO) MEMORY MATERIALS FOR NON-VOLATILE

MEMORY INTEGRATED CIRCUITS...................................................................114

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE......................................114

SEMICONDUCTOR MEMORY DEVICE ....................................................................114

FERROELECTRIC MEMORY WITH AN INTRINSIC ACCESS

TRANSISTOR COUPLED TO A CAPACITOR.....................................................114

ADAPTIVE PROGRAMMING TECHNIQUE FOR A RE-WRITABLE

CONDUCTIVE MEMORY DEVICE ......................................................................114

CROSS-POINT MEMORY ARCHITECTURE WITH IMPROVED

SELECTIVITY.........................................................................................................114

METHOD FOR FABRICATING FERROELECTRIC RANDOM

ACCESS MEMORY DEVICE.................................................................................115

BIAS-ADJUSTED MAGNETO-RESISTIVE DEVICES FOR

MAGNETIC RANDOM ACCESS MEMORY (MRAM)

APPLICATIONS......................................................................................................115

MEMORY ARRAY WITH HIGH TEMPERATURE WIRING ....................................115

SPACER CHALCOGENIDE MEMORY METHOD.....................................................115

METHOD OF AFFECTING RRAM CHARACTERISTICS BY

DOPING PCMO THIN-FILMS...............................................................................115

MRAM DEVICE INTEGRATED WITH OTHER TYPES OF

CIRCUITRY.............................................................................................................115

EPIR DEVICE AND SEMICONDUCTOR DEVICES UTILIZING

THE SAME ..............................................................................................................115

TUNNELING ANISOTROPIC MAGNETO-RESISTIVE DEVICE

AND METHOD OF OPERATION..........................................................................116

PSEUDO TUNNEL JUNCTION ..................................................................................116

TERMINAL TRAPPED CHARGE MEMORY DEVICE WITH

VOLTAGE SWITCHABLE MULTI-LEVEL RESISTANCE ................................116

DISCHARGE OF CONDUCTIVE ARRAY LINES IN FAST

MEMORY.................................................................................................................116

CROSS-POINT ARRAY USING DISTINCT VOLTAGES ..........................................116

LOW SILICON-HYDROGEN SIN LAYER TO INHIBIT

HYDROGEN-RELATED DEGRADATION IN

SEMICONDUCTOR DEVICES HAVING FERROELECTRIC

COMPONENTS.......................................................................................................116

COMPOSITIONS FOR REMOVAL OF PROCESSING BYPRODUCTS

AND METHOD FOR USING SAME................................................117

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY WITH HIGH

SELECTIVITY.........................................................................................................117

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY...........................................117

LINE DRIVERS THAT USE MINIMAL METAL LAYERS........................................117

CONDUCTIVE MEMORY STACK WITH NON-UNIFORM WIDTH .......................117

ZERO CANCELLATION SCHEME TO REDUCE PLATELINE

VOLTAGE IN FERROELECTRIC MEMORY.......................................................117

3D RRAM........................................................................................................................117

MRAM STORAGE DEVICE..........................................................................................118

METHOD OF FORMING AND USING A HARDMASK FOR

FORMING FERROELECTRIC CAPACITORS IN A

SEMICONDUCTOR DEVICE................................................................................118

HYDROGEN-LESS CVD TIN PROCESS FOR FERAM VIA0

BARRIER APPLICATION......................................................................................118

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND

CONTROL METHOD THEREOF..........................................................................118

CROSS-POINT MEMORY ARRAY EXHIBITING A

CHARACTERISTIC HYSTERESIS .......................................................................118

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND

PROGRAMMING METHOD AND ERASING METHOD

THEREOF................................................................................................................118

SERIES CONNECTED TC UNIT TYPE FERROELECTRIC RAM

AND TEST METHOD THEREOF..........................................................................119

HYDROGEN BARRIER FOR PROTECTING FERROELECTRIC

CAPACITORS IN A SEMICONDUCTOR DEVICE AND

METHODS FOR FABRICATING THE SAME .....................................................119

BRIDGE-TYPE MAGNETIC RANDOM ACCESS MEMORY (MRAM)

LATCH.....................................................................................................................119

METHOD FOR READING A PASSIVE MATRIX-ADDRESSABLE

DEVICE AND A DEVICE FOR PERFORMING THE METHOD........................119

FERROELECTRIC CAPACITOR HYDROGEN BARRIERS AND

METHODS FOR FABRICATING THE SAME .....................................................119

PATENT ANALYSIS ..................................................................................................................120

TABLE 10 NUMBER OF U.S. PATENTS GRANTED TO COMPANIES FOR

NON-VOLATILE EMERGING MEMORY TECHNOLOGIES FROM 2006

THROUGH APRIL 2010..............................................................................................................120

FIGURE 16 NUMBER OF U.S. PATENTS GRANTED TO COMPANIES FOR

NON-VOLATILE EMERGING MEMORY TECHNOLOGIES FROM 2006

THROUGH APRIL 2010..............................................................................................................121

INTERNATIONAL OVERVIEW OF U.S. PATENT ACTIVITY IN

EMERGING NON-VOLATILE RANDOM ACCESS MEMORY.......................................122

TABLE 11 NUMBER OF U.S. PATENTS GRANTED TO COMPANIES FOR

NON-VOLATILE EMERGING MEMORY PRODUCTS BY REGION FROM

2006 THROUGH APRIL 2010.....................................................................................................122

 Add 
9. COMPANY PROFILES123-142
$700.00
$350.00

COMPANY PROFILES ....................................................................................................................123

4DS, INC.....................................................................................................................................123

ADESTO TEHNOLOGIES.........................................................................................................124

ADVANCED MATERIALS INNOVATION CENTER (AMIC) ................................................124

BAE SYSTEMS PLC...................................................................................................................125

CROCUS TECHNOLOGY..........................................................................................................125

CYPRESS SEMICONDUCTOR CORPORATION....................................................................126

ELPIDA MEMORY, INC. ...........................................................................................................126

EVERSPIN TECHNOLOGIES, INC. ........................................................................................127

FUJITSU COMPONENTS AMERICA, INC. ............................................................................127

GRANDIS, INC. ..........................................................................................................................128

HEWLETT-PACKARD COMPANY...........................................................................................128

HONEYWELL INTERNATIONAL INC....................................................................................129

HYNIX SEMICONDUCTOR AMERICA INC. ..........................................................................129

INTERNATIONAL BUSINESS MACHINES (IBM) CORPORATION...................................130

IM FLASH TECHNOLOGIES, LLC..........................................................................................131

IMEC BELGIUM ........................................................................................................................131

INFINEON TECHNOLOGIES AG............................................................................................132

INNOVATIVE SILICON, INC. ..................................................................................................132

INTEL CORPORATION.............................................................................................................133

MACRONIX INTERNATIONAL CO., LTD. .............................................................................133

MATSUSHITA ELECTRIC INDUSTRIAL CORPORATION (PANASONIC)........................133

MICROMEM TECHNOLOGIES INC........................................................................................134

MICRON TECHNOLOGY, INC. ................................................................................................134

MOSYS, INC ...............................................................................................................................135

NETRINO, LLC...........................................................................................................................135

NANTERO, INC. .........................................................................................................................135

NUMONYX.................................................................................................................................136

NVE CORPORATION ................................................................................................................136

OVONYX, INC. ...........................................................................................................................137

QS SEMICONDUCTOR CORP. .................................................................................................137

RAMTRON INTERNATIONAL CORPORATION....................................................................138

RENESAS ELECTRONICS CORPORATION (HITACHI) ......................................................138

SAMSUNG SEMICONDUCTOR...............................................................................................139

SHARP LABORATORIES OF AMERICA.................................................................................140

ST MICROELECTRONICS........................................................................................................140

SYMETRIX CORPORATION.....................................................................................................140

TEXAS INSTRUMENTS INC. ...................................................................................................141

THIN FILM ELECTRONICS AB...............................................................................................141

TOSHIBA....................................................................................................................................142

UNITY SEMICONDUCTOR CORPORATION.........................................................................142

UNITY SEMICONDUCTOR CORPORATION (CONTINUED) .................................143

 Add 
10. ANNECTURE A – EXPLANATION OF TERMINOLOGIS 144-146
$105.00
$52.50

ANNEXURE A ..............................................................................................................................144

EXPLANATIONS OF TERMINOLOGIES APPLICABLE TO

CONVENTIONAL NON-VOLATILE RANDOM ACCESS MEMORY

(RAM) ...................................................................................................................................144

PROM.............................................................................................................................144

EPROM..........................................................................................................................144

EEPROM........................................................................................................................145

DRAM .............................................................................................................................145

DRAM ISSUES .................................................................................................145

SRAM.............................................................................................................................146

NVSRAM........................................................................................................................146

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